1. Field of the Invention
The present invention relates to a semiconductor device that has a low current consumption and performs high-speed operations using a low-voltage electrical source. More specifically, the present invention relates to a semiconductor device that is suitable for use in SRAM (static random access memory) and similar devices having a small standby current.
2. Description of the Related Art
In recent years, LSI (large-scale integrated circuits) and other such logic circuits have tended to operate using a low-voltage power source. The reason for this trend is that the withstanding voltage declines as the size of the transistors (abbreviated as xe2x80x9cTrxe2x80x9d hereinafter) for forming logic circuits is reduced. Accordingly, the operating voltage must be reduced as a necessity. In addition, in order to install LSIs in portable information devices, it is essential for these LSI to be capable of being operated by the battery devices and therefore, these LSIs must be operated at low voltage region and in low power consumption.
However, there has also been a growing demand to increase the speed of operation of LSIs. Thus, it is not acceptable for the speed of operations to decrease in order to accomplish low voltage operation. In order to accomplish high-speed operation of a transistor while using a low voltage power source, a measure can be taken to reduce the amount of delay by lowering the transistor""s threshold voltage (denoted as xe2x80x9cVtxe2x80x9d hereinafter). Thus, as one example of conventional semiconductor devices, there is a design in which all of the circuits on a pass required to provide a high speed are formed of transistors having a low threshold voltage (referred to as xe2x80x9cConventional Example 1xe2x80x9d hereinafter).
However, when the threshold voltage is reduced to enable high speed operation of the transistor, the transistor can no longer cut-off sufficiently. As a result, even in a no-bias state where the voltage between gate sources is xe2x80x9c0xe2x80x9d, a leak current, referred to as a xe2x80x9csub-threshold currentxe2x80x9d, will flow into the transistor. In the case of products typified by a low-power consuming SRAM in which there are many transistors and the standby current is very small, this sub-threshold current is too large to be ignored. However, if the threshold voltage of the transistor is raised in order to reduce the leak current, then a longer delay results, and an improvement in speed cannot be anticipated. Thus, in order to operate a semiconductor device at high speed with a low current consumption using a low voltage power source, it is necessary to satisfy the opposing requirements of reducing the transistor""s threshold voltage and decreasing the leak current.
A design (referred to as xe2x80x9cConventional Example 2xe2x80x9d hereinafter) such as shown in FIG. 10 in which improvements have been added to Conventional Example 1 may be considered as a semiconductor device in which the effects from sub-threshold current have been eliminated. The semiconductor device of Conventional Example 2 is based on the technical concept disclosed in Japanese Patent Application, First Publication No. Hei 6-208790, and realizes four stages of inverters in a dependent connection. In this semiconductor device, only the threshold voltage of transistors that are ON in the standby state, in which logic circuits are not operated, has been reduced. Note that the example shown in the figure assumes that the electric potential of input node A in the standby state is at xe2x80x9cLxe2x80x9d level.
More specifically, with respect to the transistors forming the first inverter stage which is connected to input node A, the p-type (p-channel) transistor (MOSFET: metal oxide field effect transistor) Q101 is a low Vt transistor having a low threshold voltage, while the n-type (n-channel) TrQ102 is a high Vt transistor having a high threshold voltage. Note that the term xe2x80x9chigh Vtxe2x80x9d as employed here device that the threshold voltage is higher than that of TrQ101, and does not specifically mean a transistor in which the threshold voltage has been increased. Accordingly, if sub-threshold currents can be blocked, then TrQ102 can be formed using normal Vt transistors which do not change their threshold voltages. Since the distinction between n-type and p-type transistors is clear from the figures, they will not be discussed separately in the explanation that follows.
TrQ103xcx9cTrQ108 are identical to TrQ101 and TrQ102. TrQ103 and TrQ107 are the high Vt transistors and TrQ104 and TrQ108 are the low Vt transistors positioned at the second and final stages of inverters. The levels of the electric potentials at nodes A, A1, A2 and A3 in the standby state in FIG. 10 are xe2x80x9cLxe2x80x9d, xe2x80x9cHxe2x80x9d, xe2x80x9cLxe2x80x9d, and xe2x80x9cHxe2x80x9d, respectively. In other words, the transistors that cut-off in the standby state are TrQ102, TrQ103, TrQ106 and TrQ107. However, since these are all high Vt transistors, the subthreshold current is small. Accordingly, leak currents while in the standby state do not pose a problem as was the case in Conventional Example 1.
However, Conventional Example 2 has the following problems. Namely, high-speed operation is possible when the semiconductor device is in the active state for operating the internal logic circuits, since TrQ101, TrQ104, TrQ105, and TrQ108 are low Vt transistors as in Conventional Example 1. Accordingly, low Vt TrQ101 is ON when the input signal to input node A is falling, and the electric potential of node A1 changes at high speed as a result. Conversely, high Vt TrQ102 is ON when the input signal to node A is rising. In this case, the electric potential of node A1 changes at low speed as compared to the case where the signal is falling, since the gate capacitance of a high Vt transistor is greater than that of a low Vt transistor.
Accordingly, the aforementioned Japanese Unexamined Patent Application, First Publication No. Hei 6-208790 broadens the channel width of the high Vt transistors so that the electric potential of node A1 changes at high speed when there is a rising signal input to input node A. However, it is necessary to increase the size of the transistor in order to increase the channel width. Thus, there is an increase in chip size in a semiconductor device having a design such as conventional example 2.
A semiconductor device (xe2x80x9cconventional example 3xe2x80x9d hereinafter) such as shown in FIG. 11 may be considered as a device of eliminating the effects of the sub-threshold current that was cited in the conventional example 1. As in the case of conventional example 2, the semiconductor device according to conventional example 3 is an example of the application of the technology disclosed in Japanese Patent Application, First Publication No. Hei 8-228145 to a design in which there are four stages of inverters. In FIG. 11, all of the transistors for the logic circuits on the pass from input node A to the output node B which must be high speed are formed of low Vt transistors. Namely, the conventional example 3 is identical to the conventional example 1 in this regard. In FIG. 11, low Vt TrQ112, TrQ113, TrQ116, and TrQ117 are employed in place of the high Vt TrQ102, TrQ103, TrQ106 and TrQ107 that are shown in FIG. 10.
In addition, high Vt TrQ120 and TrQ121 are provided in FIG. 11. Of these, TrQ120 is inserted in between the electric potential of the electric source and the source terminal for TrQ101, etc. The ON/OFF state of TrQ120 is controlled by chip selecting signal /CS which is connected to the gate terminal. TrQ121 is inserted in between the grounding electric potential and the source terminal for TrQ112, etc., and its ON/OFF state is controlled by a chip selecting signal CS that is connected to the gate terminal. Note that chip selecting signal CS is set at xe2x80x9cHxe2x80x9d level when the semiconductor device is in the active state shown in the figure, and is set at xe2x80x9cLxe2x80x9d level when the semiconductor device is in the standby state. The symbol xe2x80x9c/xe2x80x9d which precedes the signal name indicates an inverted signal. Thus, chip selecting signal /CS is the inverted signal of chip selecting signal CS.
When the semiconductor device shown in FIG. 11 is in the standby state and chip selecting signals CS and /CS are at xe2x80x9cLxe2x80x9d and xe2x80x9cHxe2x80x9d levels respectively, then both TrQ120 and TrQ121 are cut-off. As a result, the sub-threshold current that flows to the low Vt transistors that form the inverter is stopped by these high Vt transistors. On the other hand, when the semiconductor device is in the active state and chip selecting signals CS and /CS are at xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d levels respectively, then TrQ120 and TrQ121 both enter the ON state. In this case, the sub-threshold current is sufficiently low enough when compared to the operating current that it may be ignored. In the explanation that follows below, transistors like TrQ120 and TrQ121 which block the sub-threshold current will be referred to as xe2x80x9cpower cutting transistorsxe2x80x9d.
The semiconductor device of the conventional example 3 has the following problems however. Namely, in the circuit design of the conventional example 3, when the semiconductor device is in the standby state, a high impedance state results because the supply of electric potential from TrQ117 and TrQ108 to output node B is blocked. For this reason, the electric potential output from the semiconductor device becomes unstable. Therefore, in order to stabilize the electric potential of output node B in the semiconductor device of Conventional Example 3, it is necessary to provide a design that maintains the state that is present immediately before the device shifts from active to standby state. This is accomplished by providing a maintaining device such as a latch or flip-flop. However, the circuit design in the semiconductor device of Conventional Example 3 becomes complicated in this case, and the chip size is increased as a result.
The design shown in FIG. 12 may be considered as a semiconductor device that resolves these problems (referred to as xe2x80x9cConventional Example 4xe2x80x9d hereinafter). This is the semiconductor device disclosed in such references as the aforementioned Japanese Unexamined Patent Application, First Publication No. Hei 6-208790; Switched-Source-Impedance CMOS Circuit for Low Standy Subthreshold Current Giga-Scale LSI""s, Masashi Horiguchi et. al, Proceeding of the VSLI symposium papers, pp. 47-48 (1993); and Standby/Active Mode Logic for Sub-1 V 1G/4Gb DRAMS, Daisaburo Takashima et. al, Proceeding of the VSLI symposium papers, pp. 83-84 (1993).
FIG. 12 differs from FIG. 11 on the following point. Namely, of the n-type and p-type transistors forming each of the inverters in FIG. 12, only one of the transistors that cuts-off in the standby state is connected to TrQ120 or TrQ121. As a result, the sub-threshold current that is problematic in the standby state does not flow to these transistors. Note that FIG. 12 also assumes the case where the electric potential of input node A in the standby state is at xe2x80x9cLxe2x80x9d level. Namely, only TrQ112, TrQ113, TrQ116 and TrQ117 are cut-off in the standby state.
For this reason, the source terminals of TrQ101 and TrQ105 are directly connected to the power source electric potential, rather than being connected to the source terminal of TrQ120. In addition, in the same figure, the source terminals of TrQ104 and TrQ108 are directly connected to the grounding electric potential, rather than to the drain terminal of TrQ121. As a result, the xe2x80x9cHxe2x80x9d, xe2x80x9cLxe2x80x9d, xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d levels from, respectively, TrQ101, TrQ104, TrQ105, and TrQ108 which are in the ON state continue to be supplied to nodes A1, A2, A3 and B, even when the device is in the standby state. Thus, the electric potential of output node B does not become unstable in Conventional Example 4, and it is not necessary to provide a maintaining device in front of output node B as was the case with Conventional Example 3.
However, the semiconductor device of this conventional example 4 has the following problems. Namely, in the design of Conventional Example 4, the delay time will differ depending on the frequency of the signal input to the semiconductor device. Specifically, the greater the number of high frequency signals (also referred to as a xe2x80x9cshort pulsexe2x80x9d below) that are input, the larger the increase in the delay time from input node A to output node B as compared to the case where low frequency signals are input to input node A. This point will be discussed further below.
The cycle of the signal input to input node A is designated as time Tcycle, and the propagation delay time until this input signal is output from output node B is designated as time Tpd as shown in FIGS. 13A-13C. Note that the symbols VA and VB in this figure are the electric potentials of input node A and output node B respectively. Symbol In is the value of the current flowing to TrQ120. As shown by time t101xcx9ct103, a signal is input for a low frequency signal that satisfies cycle T1 (=Tcycle)xe2x89xa7time Tpd.
If a rising input signal is considered in this case for example, then TrQ112, TrQ113, TrQ116, and TrQ117 in FIG. 12 are sequentially turned ON, and, in parallel, TrQ101, TrQ104, TrQ105, and TrQ108 are sequentially turned OFF. Note that this also applies to the case where the input signal is falling. Namely, in this case, the ON/OFF state of each transistor is the opposite of the case where the signals are rising. Further, once time Tpd has passed from time t101 to time t102, then the signal input to input node A is output from output node B. Accordingly, if an input signal for cycle T1 is supplied thereafter, then a rise in the input signal during the next cycle appears at time t103. The events as described above are repeatedly carried out.
In summary, when a low frequency input signal is provided, only one of the four n-type and p-type low Vt transistors is charged and discharged at any time t considered. Accordingly, for example, the value In of the current flowing in TrQ120 changes at roughly equal time intervals to match the charge and discharge of the n-type transistor, as shown in FIGS. 13A-13C. The current value In at peak is roughly the same. Note that FIGS. 13A-13C shows the case where there are more stages of inverters connected than in the semiconductor device shown in FIG. 12, and depicts the case in which current In repetitively changes.
On the other hand, as shown by times t103xcx9ct104 in FIGS. 13A-13C, a short pulse satisfying cycle Ts (=Tcycle) less than time Tpd was input as a high frequency signal. In this case, the input signal which was rising at time t103 is output from output node B at time t105. Accordingly, this signal is still propagating inside the semiconductor device at time t104. Thus, when the input signal again rises at time t104 and is input to the initial inverter, two low Vt transistors are simultaneously charged and discharged in the semiconductor device. For this reason, the current that flows to TrQ120 for example, increases as compared to when the frequency of the input signal is low, as shown by times t104xcx9ct105 in FIGS. 13A-13C. Thus, the rise and fall in the electric potential at the source terminals for TrQ112, 113, 116 and 117 (i.e., the electric potential at nodes CN and CP) becomes larger, and the propagation delay time Tpd increases as a result.
FIGS. 14 and 15 show the results of simulations performed by the present inventor employing 24 stages of inverters. FIG. 14 shows the case wherein a low frequency input signal was provided. The notation xe2x80x9cINxe2x80x9d shown in the figure is a signal waveform that is input to an input node A. The rising portion of this waveform is a long period signal that can be illustrated in the figure. In addition, xe2x80x9cA1xe2x80x9d, xe2x80x9cA9xe2x80x9d and xe2x80x9cA17xe2x80x9d are the respective signal waveforms output from the first, 9th and 17th stages of inverters.
Note that in actuality these signals are inverted with respect to input signal IN. However, for convenience, they have been fitted to the depiction of input signal IN in the figure. The notation xe2x80x9cOUTxe2x80x9d shown in the figure is a signal waveform output from output node B. As may be understood from the figure, the delay time in this case is approximately 7.2 seconds. In addition, xe2x80x9cIpxe2x80x9d and xe2x80x9cInxe2x80x9d in the figure indicate the signal waveform of the current flowing to TrQ120 and TrQ121, respectively. xe2x80x9cIpxe2x80x9d and xe2x80x9cInxe2x80x9d change corresponding to the sequential propagation of the input signal through each stage of the inverters. The peak of the current value is roughly the same at each stage of inverters.
On the other hand, FIG. 15 shows the case where a short pulse is provided as an input signal. xe2x80x9cINxe2x80x9d in the figure is the input signal waveform in the next cycle that follows the previously input [IN]. Similarly, [A1]xe2x80x2 and [A9xe2x80x2] are the signal waveforms respectively output from the first and 9th stages of inverters corresponding to input signal INxe2x80x2. In this case, the cycle of input signal IN is 4 ns, which is relatively short as compared to the 7 ns propagation delay time of the semiconductor device. For this reason, from the time at 4 ns when input signal INxe2x80x2 is input, until the time at 7.5 ns when input signal IN is output from output node B (xe2x80x9cOUTxe2x80x9d in the figures), the absolute value of currents In and Ip is increasing as compared to when outside this time range. As a result, approximately 7.5 ns are required until input signal IN is output as output OUT. Thus, the propagation delay time Tpd has increased about 0.3 ns (or approximately 5%) as compared to the case in FIG. 14.
The present invention has been carried out in consideration of the above-described points, and has as its objective the provision of a semiconductor device which can operate at high speed using low power voltage, has low power consumption, does not require additional circuits in order to stabilize the electric potential in the standby state, and which is not effected by a delay time that depends on the frequency of the input signal.
In order to resolve the above-described problems, the present invention according to the first aspect is a semiconductor device that is provided with power cutting transistor for blocking leak currents from the logic circuit transistors forming a logic circuit that cut off when the circuit is in the standby state, in which the threshold voltage of the logic circuit transistors is lower than the threshold voltage of the power cutting transistors. This semiconductor device is characterized in that a plurality of these power cutting transistors is provided for each type of transistor, and several power cutting transistors are assigned by transistor type to the transistors of the logic circuit.
The invention according to the second aspect is characterized in that in the invention according to the first aspect, the various power cutting transistors are assigned to each part of the circuit so that the number of logic circuit transistors charging and discharging simultaneously is a maximum of one.
The invention according to the third aspect is characterized in that in the invention according to the first aspect, the one to a plurality of logic circuit transistors that are assigned to each power cutting transistor is determined according to the minimum cycle during which an input signal supplied to the logic circuit can be taken up.
The invention according to the fourth aspect is characterized in that in the invention according to the third aspect, the portion of the circuit that is formed of the one to a plurality of logic circuit transistors that are assigned to each power cutting transistor is determined so that the delay time Td for that portion of the circuit satisfies Tcycxe2x89xa7Td, where Tcycle is the minimum cycle for obtaining the input signal.
The invention according to the fifth aspect is characterized in that in the invention according to the first aspect, the number of logic circuit transistors assigned per power cutting transistor is reduced as the output stage is approached, as compared to when near the input stage of the logic circuit.
The invention of the sixth aspect is characterized in that in the invention according to one of the first aspect, the power cutting transistors are turned ON and OFF together according to a chip selecting signal for setting the logic circuit to the active or standby state, and in that a buffering device is inserted in between the power cutting transistors for buffering the chip selecting signal as the chip selecting signal is being distributed to each power cutting transistor.
The invention of the seventh aspect is characterized in that a semiconductor memory device for recording data in memory cells that form a memory cell array is provided with a buffering device for buffering an address signal input from the outside; a row decoding device for decoding the row address included in the address signal and activating a word line in the memory cell array, while also detecting a transformation in the row address, and outputting a row address transformation detecting signal; a column decoding device for decoding a column address included in the address signal and generating a selecting signal for the bit line in the memory cell array, while also detecting a transformation in the column address and outputting a column address transformation detecting signal; a sensing device for sensing the electric potential which is generated by reading out on the bit line the data in the memory cell that is designated by the address signal, and outputting the data; an input/output data controlling device for giving and receiving data between the sensing device and the outside; and a timing signal generating device for generating a timing signal for operating the row decoding device, the column decoding device and the sensing device, based on the row address transformation detecting signal and the column address transformation detecting signal; wherein at least one of the aforementioned device is formed of a semiconductor device according to one of claims 1 through 6.